`timescale 1ns / 1ns

module huawei7 (
    input  wire clk,
    input  wire rst,
    output reg  clk_out
);
    reg [1:0] stat;
    initial begin
        stat <= 0;
        clk_out <= 0;
    end

    always @(posedge clk or negedge rst) begin
        if (rst == 0) begin
            clk_out <= 0;
            stat <= 0;
        end else begin
            clk_out <= (stat == 0);
            stat <= stat + 1;
        end
    end
endmodule
